An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/GargCSK06
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/GargCSK06
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Milagros_Sashik%E2%88%9A%C2%B0nth
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/V._Kamakoti_0001
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Vikram_Chandrasekhar
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Vivek_Garg
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FVLSID.2006.38
>
foaf:
homepage
<
https://doi.org/10.1109/VLSID.2006.38
>
dc:
identifier
DBLP conf/vlsid/GargCSK06
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FVLSID.2006.38
(xsd:string)
dcterms:
issued
2006
(xsd:gYear)
rdfs:
label
An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Milagros_Sashik%E2%88%9A%C2%B0nth
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/V._Kamakoti_0001
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Vikram_Chandrasekhar
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Vivek_Garg
>
swrc:
pages
507-510
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2006
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/vlsid/GargCSK06/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/vlsid/GargCSK06
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/vlsid/vlsid2006.html#GargCSK06
>
rdfs:
seeAlso
<
https://doi.org/10.1109/VLSID.2006.38
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/vlsid
>
dc:
title
An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document