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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/GuptaA98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aarti_Gupta>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pranav_Ashar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1998.646606>
foaf:homepage <https://doi.org/10.1109/ICVD.1998.646606>
dc:identifier DBLP conf/vlsid/GuptaA98 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1998.646606 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
rdfs:label Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aarti_Gupta>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pranav_Ashar>
swrc:pages 222-225 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1998>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/GuptaA98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/GuptaA98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1998.html#GuptaA98>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1998.646606>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject Boolean satisfiability (SAT), Binary Decision Diagrams (BDDs), ATPG techniques, combinational circuits, circuit similarity, combinational equivalence checking, formal verification. (xsd:string)
dc:title Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document