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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/GuyotRHL96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alain_Guyot>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bachar_El-Hassan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marc_Renaudin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Volker_Levering>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1996.489638>
foaf:homepage <https://doi.org/10.1109/ICVD.1996.489638>
dc:identifier DBLP conf/vlsid/GuyotRHL96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1996.489638 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Self timed division and square-root extraction. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alain_Guyot>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bachar_El-Hassan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marc_Renaudin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Volker_Levering>
swrc:pages 376-381 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/GuyotRHL96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/GuyotRHL96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1996.html#GuyotRHL96>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1996.489638>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject pipeline arithmetic; dividing circuits; integrated circuit design; iterative methods; self-timed integrated circuit; square-root extraction; mathematical algorithm; design methodology; functional blocks; logic level; quotient; binary notation; division; pipelined arithmetic (xsd:string)
dc:title Self timed division and square-root extraction. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document