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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/HonkoteT10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Baris_Taskin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vinayak_Honkote>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI.Design.2010.71>
foaf:homepage <https://doi.org/10.1109/VLSI.Design.2010.71>
dc:identifier DBLP conf/vlsid/HonkoteT10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI.Design.2010.71 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Baris_Taskin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vinayak_Honkote>
swrc:pages 218-223 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/HonkoteT10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/HonkoteT10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#HonkoteT10>
rdfs:seeAlso <https://doi.org/10.1109/VLSI.Design.2010.71>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject Resonant clocking, Low power, Capacitive load balancing, Optimization, Spice (xsd:string)
dc:title Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document