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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/JacommePB99>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fr%E2%88%9A%C2%A9d%E2%88%9A%C2%A9ric_P%E2%88%9A%C2%A9trot>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ludovic_Jacomme>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajesh_K._Bawa>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1999.745140>
foaf:homepage <https://doi.org/10.1109/ICVD.1999.745140>
dc:identifier DBLP conf/vlsid/JacommePB99 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1999.745140 (xsd:string)
dcterms:issued 1999 (xsd:gYear)
rdfs:label Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fr%E2%88%9A%C2%A9d%E2%88%9A%C2%A9ric_P%E2%88%9A%C2%A9trot>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ludovic_Jacomme>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajesh_K._Bawa>
swrc:pages 151-156 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1999>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/JacommePB99/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/JacommePB99>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1999.html#JacommePB99>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1999.745140>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document