Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/KrishnanGEK03
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Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks.
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Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks.
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