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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/KumarFP95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kevin_E._Forward>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marimuthu_Palaniswami>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Suthikshn_Kumar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1995.512077>
foaf:homepage <https://doi.org/10.1109/ICVD.1995.512077>
dc:identifier DBLP conf/vlsid/KumarFP95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1995.512077 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label A fast-multiplier generator for FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kevin_E._Forward>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marimuthu_Palaniswami>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Suthikshn_Kumar>
swrc:pages 53-56 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/KumarFP95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/KumarFP95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#KumarFP95>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1995.512077>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject multiplying circuits; field programmable gate arrays; neural chips; parallel architectures; fast-multiplier generator; FPGAs; artificial neural networks; variable word length multipliers; Booth encoded optimized Wallace tree architecture; FPGA architecture (xsd:string)
dc:title A fast-multiplier generator for FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document