Formal synthesis of circuits with a simple handshake protocol.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/KumarKS95
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1995
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Formal synthesis of circuits with a simple handshake protocol.
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formal logic; logic design; protocols; high level synthesis; formal circuit synthesis; handshake protocol; preproven building blocks; template; operator semantics; correctness proofs; higher-order temporal operators; parametrized data signals; HOL theorem prover; sequentially composed modules; parallel module composition; synchronous circuits
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Formal synthesis of circuits with a simple handshake protocol.
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