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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/LambrechtsRJCV08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andy_Lambrechts>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Diederik_Verkest>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Francky_Catthoor>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Murali_Jayapala>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Praveen_Raghavan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI.2008.25>
foaf:homepage <https://doi.org/10.1109/VLSI.2008.25>
dc:identifier DBLP conf/vlsid/LambrechtsRJCV08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI.2008.25 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andy_Lambrechts>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Diederik_Verkest>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Francky_Catthoor>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Murali_Jayapala>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Praveen_Raghavan>
swrc:pages 201-207 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/LambrechtsRJCV08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/LambrechtsRJCV08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2008.html#LambrechtsRJCV08>
rdfs:seeAlso <https://doi.org/10.1109/VLSI.2008.25>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject Energy-Aware Design, Low Power, Processor Architecture, Interconnect-Aware Design (xsd:string)
dc:title Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document