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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/MangalDBP07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Raghavendra_B._Deshmukh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rahul_M._Badghare>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajendra_M._Patrikar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sanjiv_Kumar_Mangal>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSID.2007.85>
foaf:homepage <https://doi.org/10.1109/VLSID.2007.85>
dc:identifier DBLP conf/vlsid/MangalDBP07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSID.2007.85 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label FPGA Implementation of Low Power Parallel Multiplier. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Raghavendra_B._Deshmukh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rahul_M._Badghare>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajendra_M._Patrikar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sanjiv_Kumar_Mangal>
swrc:pages 115-120 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/MangalDBP07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/MangalDBP07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2007.html#MangalDBP07>
rdfs:seeAlso <https://doi.org/10.1109/VLSID.2007.85>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title FPGA Implementation of Low Power Parallel Multiplier. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document