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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/MehtaES97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kent_L._Einspahr>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sharad_C._Seth>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shashank_K._Mehta>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1997.568090>
foaf:homepage <https://doi.org/10.1109/ICVD.1997.568090>
dc:identifier DBLP conf/vlsid/MehtaES97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1997.568090 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label Synthesis for Testability by Two-Clock Control. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kent_L._Einspahr>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sharad_C._Seth>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shashank_K._Mehta>
swrc:pages 279-283 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/MehtaES97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/MehtaES97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1997.html#MehtaES97>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1997.568090>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject timing, synthesis for testability, two-clock control scheme, sequential circuit, logic synthesis, finite state machine, split coding system, encoding, Hamiltonian cycle, state transition graph, FSM benchmark (xsd:string)
dc:title Synthesis for Testability by Two-Clock Control. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document