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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/MohanMC97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chunduri_Rama_Mohan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Partha_Pal_Chaudhuri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Srobona_Mitra>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1997.568207>
foaf:homepage <https://doi.org/10.1109/ICVD.1997.568207>
dc:identifier DBLP conf/vlsid/MohanMC97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1997.568207 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chunduri_Rama_Mohan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Partha_Pal_Chaudhuri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Srobona_Mitra>
swrc:pages 547-563 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/MohanMC97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/MohanMC97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1997.html#MohanMC97>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1997.568207>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject built-in self test, BIST, fully testable controllers, full scan, partial scan, testing scheme, ATPGs, testability, FSMs, RTL designs, cellular automata, VERILOG, VHDL, stuck-at fault model, SYNERGY, Cadence, target library, area overhead (xsd:string)
dc:title On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document