Synchronous Controller Models for Synthesis from Communicating VHDL Processes.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/NarasimhanVR96
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Synchronous Controller Models for Synthesis from Communicating VHDL Processes.
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Synchronous Controller Models for Synthesis from Communicating VHDL Processes.
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