Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/NowickJC95
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1995
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Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.
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asynchronous circuits; design for testability; hazards and race conditions; minimisation of switching nets; delays; redundancy; logic design; combinational circuits; logic testing; multivalued logic circuits; asynchronous circuits; stuck-at fault testability; robust path delay fault testability; multilevel logic; hazard-free logic; synthesis for testability method; multi-level circuit; minimization algorithms; area overhead
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Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.
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