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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/NowickJC95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fu-Chiung_Cheng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Niraj_K._Jha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Steven_M._Nowick>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1995.512099>
foaf:homepage <https://doi.org/10.1109/ICVD.1995.512099>
dc:identifier DBLP conf/vlsid/NowickJC95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1995.512099 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fu-Chiung_Cheng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Niraj_K._Jha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Steven_M._Nowick>
swrc:pages 171-176 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/NowickJC95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/NowickJC95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#NowickJC95>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1995.512099>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject asynchronous circuits; design for testability; hazards and race conditions; minimisation of switching nets; delays; redundancy; logic design; combinational circuits; logic testing; multivalued logic circuits; asynchronous circuits; stuck-at fault testability; robust path delay fault testability; multilevel logic; hazard-free logic; synthesis for testability method; multi-level circuit; minimization algorithms; area overhead (xsd:string)
dc:title Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document