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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/PatraF95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Donald_S._Fussell>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Priyadarsan_Patra>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1995.512093>
foaf:homepage <https://doi.org/10.1109/ICVD.1995.512093>
dc:identifier DBLP conf/vlsid/PatraF95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1995.512093 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Fully asynchronous, robust, high-throughput arithmetic structures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Donald_S._Fussell>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Priyadarsan_Patra>
swrc:pages 141-145 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/PatraF95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/PatraF95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#PatraF95>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1995.512093>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject digital arithmetic; adders; multiplying circuits; asynchronous circuits; VLSI; integrated logic circuits; fully asynchronous structures; high-throughput arithmetic structures; bit serial adders; bit serial multipliers; delay-insensitive; RSA cryptosystems; scaleability (xsd:string)
dc:title Fully asynchronous, robust, high-throughput arithmetic structures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document