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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/PoornaiahM96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/D._V._Poornaiah>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/P._V._Ananda_Mohan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1996.489458>
foaf:homepage <https://doi.org/10.1109/ICVD.1996.489458>
dc:identifier DBLP conf/vlsid/PoornaiahM96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1996.489458 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/D._V._Poornaiah>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/P._V._Ananda_Mohan>
swrc:pages 69-72 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/PoornaiahM96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/PoornaiahM96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1996.html#PoornaiahM96>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1996.489458>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject VLSI; multiplying circuits; adders; video coding; data compression; computational complexity; digital signal processing chips; VLSI; concurrent dual multiplier-dual adder architecture; video coding applications; high-throughput image coding; carry-save 4:2 compressors; computation time (xsd:string)
dc:title A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document