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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/PotlapallyHRLC01>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anand_Raghunathan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ganesh_Lakshminarayana>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michael_S._Hsiao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nachiketh_R._Potlapally>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Srimat_T._Chakradhar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.2001.902666>
foaf:homepage <https://doi.org/10.1109/ICVD.2001.902666>
dc:identifier DBLP conf/vlsid/PotlapallyHRLC01 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.2001.902666 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
rdfs:label Accurate Power Macro-modeling Techniques for Complex RTL Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anand_Raghunathan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ganesh_Lakshminarayana>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michael_S._Hsiao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nachiketh_R._Potlapally>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Srimat_T._Chakradhar>
swrc:pages 235-241 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2001>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/PotlapallyHRLC01/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/PotlapallyHRLC01>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2001.html#PotlapallyHRLC01>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.2001.902666>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title Accurate Power Macro-modeling Techniques for Complex RTL Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document