[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/PrasadR95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/S._C._Prasad>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1995.512129>
foaf:homepage <https://doi.org/10.1109/ICVD.1995.512129>
dc:identifier DBLP conf/vlsid/PrasadR95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1995.512129 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Circuit optimization for minimisation of power consumption under delay constraint. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/S._C._Prasad>
swrc:pages 305-309 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/PrasadR95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/PrasadR95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#PrasadR95>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1995.512129>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject VLSI; delays; minimisation; circuit optimisation; capacitance; logic gates; logic design; integrated circuit layout; CMOS logic circuits; logic CAD; circuit layout CAD; circuit optimization; power consumption minimisation; delay constraint; VLSI circuits; CMOS gates; internal capacitances; series-connected transistors; multipass algorithm; transistor reordering (xsd:string)
dc:title Circuit optimization for minimisation of power consumption under delay constraint. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document