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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/RaghunathanAM95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anand_Raghunathan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pranav_Ashar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sharad_Malik>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1995.512086>
foaf:homepage <https://doi.org/10.1109/ICVD.1995.512086>
dc:identifier DBLP conf/vlsid/RaghunathanAM95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1995.512086 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Test generation for cyclic combinational circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anand_Raghunathan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pranav_Ashar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sharad_Malik>
swrc:pages 104-109 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/RaghunathanAM95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/RaghunathanAM95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#RaghunathanAM95>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1995.512086>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject combinational circuits; logic testing; fault diagnosis; automatic testing; integrated circuit testing; network topology; cyclic combinational circuits; combinational logic circuits; bus structures; data paths; single-stuck-at fault test pattern; test pattern generators; test generation problem; fault coverage; formal analysis; untestable faults; testing algorithm; program RAM (xsd:string)
dc:title Test generation for cyclic combinational circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document