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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/RudnickP97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Elizabeth_M._Rudnick>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Janak_H._Patel>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1997.568183>
foaf:homepage <https://doi.org/10.1109/ICVD.1997.568183>
dc:identifier DBLP conf/vlsid/RudnickP97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1997.568183 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Elizabeth_M._Rudnick>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Janak_H._Patel>
swrc:pages 495-503 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/RudnickP97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/RudnickP97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1997.html#RudnickP97>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1997.568183>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject logic CAD, serial logic simulation bottleneck, parallel fault simulation, sequential circuit fault simulation algorithms, parallel architectures, fault-partitioning approach, speedup, test set partitioning, benchmark circuits, fault coverage (xsd:string)
dc:title Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document