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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/SaldanhaSBS95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alberto_L._Sangiovanni-Vincentelli>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alexander_Saldanha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Narendra_V._Shenoy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Robert_K._Brayton>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1995.512084>
foaf:homepage <https://doi.org/10.1109/ICVD.1995.512084>
dc:identifier DBLP conf/vlsid/SaldanhaSBS95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1995.512084 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Functional clock schedule optimization. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alberto_L._Sangiovanni-Vincentelli>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alexander_Saldanha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Narendra_V._Shenoy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Robert_K._Brayton>
swrc:pages 93-98 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/SaldanhaSBS95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/SaldanhaSBS95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#SaldanhaSBS95>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1995.512084>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject clocks; scheduling; delays; flip-flops; sequential circuits; timing; circuit optimisation; clock schedule optimization; delays; latches; false paths; time frames; level-sensitive sequential circuits (xsd:string)
dc:title Functional clock schedule optimization. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document