Status Condition Analysis during Data Path Verification of Sequential Circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/Sarkar00
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Value
dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/Sarkar00
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Dipankar_Sarkar_0001
>
foaf:
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<
http://dx.doi.org/doi.org%2F10.1109%2FICVD.2000.812587
>
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dcterms:
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2000
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rdfs:
label
Status Condition Analysis during Data Path Verification of Sequential Circuits.
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foaf:
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rdfs:
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https://dblp.l3s.de/d2r/resource/conferences/vlsid
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title
Status Condition Analysis during Data Path Verification of Sequential Circuits.
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