[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/SaxenaPL99>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._L._Liu_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peichen_Pan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Prashant_Saxena>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1999.745189>
foaf:homepage <https://doi.org/10.1109/ICVD.1999.745189>
dc:identifier DBLP conf/vlsid/SaxenaPL99 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1999.745189 (xsd:string)
dcterms:issued 1999 (xsd:gYear)
rdfs:label The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._L._Liu_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peichen_Pan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Prashant_Saxena>
swrc:pages 402-407 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1999>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/SaxenaPL99/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/SaxenaPL99>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1999.html#SaxenaPL99>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1999.745189>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document