Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/ShahS96
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1996
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Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs.
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Interconnect, buffer, drivers, repeaters, sizing, dynamic programming, power-delay tradeoffs, sensitivity
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Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs.
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