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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/SherigarMKD98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/A._S._Mahadevan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_S._Sumam>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/K._Senthil_Kumar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/M._Bhaskar_Sherigar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1998.646640>
foaf:homepage <https://doi.org/10.1109/ICVD.1998.646640>
dc:identifier DBLP conf/vlsid/SherigarMKD98 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1998.646640 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
rdfs:label A Pipelined Parallel Processor to Implement MD4 Message Digest Algorithm on Xilinx FPGA. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/A._S._Mahadevan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_S._Sumam>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/K._Senthil_Kumar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/M._Bhaskar_Sherigar>
swrc:pages 394-399 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1998>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/SherigarMKD98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/SherigarMKD98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1998.html#SherigarMKD98>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1998.646640>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title A Pipelined Parallel Processor to Implement MD4 Message Digest Algorithm on Xilinx FPGA. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document