Macro Block Based FPGA Floorplanning. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Akash_Randhar>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Dinesh_Bhatia>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Jianzhong_Shi>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FICVD.1997.567955>
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dc:identifier	DBLP conf/vlsid/ShiRB97 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FICVD.1997.567955 (xsd:string)
dcterms:issued	1997 (xsd:gYear)
rdfs:label	Macro Block Based FPGA Floorplanning. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Akash_Randhar>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Dinesh_Bhatia>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Jianzhong_Shi>
swrc:pages	21-26 (xsd:string)
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owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/vlsid/ShiRB97>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/vlsid/vlsid1997.html#ShiRB97>
rdfs:seeAlso	<https://doi.org/10.1109/ICVD.1997.567955>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject	integrated circuit layout, macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, ASIC design, large benchmark examples, VLSI floorplanning, heuristic algorithm (xsd:string)
dc:title	Macro Block Based FPGA Floorplanning. (xsd:string)
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rdf:type	swrc:InProceedings
rdf:type	foaf:Document