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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/ShrivastavMRVAFHE01>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._Fink>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/G._Shrivastav>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/I._Eisele>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J._Vasi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/K._G._Anil>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/S._Mahapatra>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/V._Ramgopal_Rao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Walter_Hansch>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.2001.902703>
foaf:homepage <https://doi.org/10.1109/ICVD.2001.902703>
dc:identifier DBLP conf/vlsid/ShrivastavMRVAFHE01 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.2001.902703 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
rdfs:label erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._Fink>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/G._Shrivastav>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/I._Eisele>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J._Vasi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/K._G._Anil>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/S._Mahapatra>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/V._Ramgopal_Rao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Walter_Hansch>
swrc:pages 475-478 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2001>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/ShrivastavMRVAFHE01/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/ShrivastavMRVAFHE01>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2001.html#ShrivastavMRVAFHE01>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.2001.902703>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document