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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/SinghKK96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anshul_Kumar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jaswinder_Pal_Singh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shashi_Kumar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1996.489622>
foaf:homepage <https://doi.org/10.1109/ICVD.1996.489622>
dc:identifier DBLP conf/vlsid/SinghKK96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1996.489622 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label A multiplier generator for Xilinx FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anshul_Kumar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jaswinder_Pal_Singh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shashi_Kumar>
swrc:pages 322-323 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/SinghKK96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/SinghKK96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1996.html#SinghKK96>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1996.489622>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject multiplying circuits; field programmable gate arrays; high level synthesis; circuit CAD; table lookup; sequential circuits; combinational circuits; pipeline processing; integrated circuit design; digital arithmetic; carry logic; multiplier generator; Xilinx FPGAs; module generator; multiplier designs; LUT based FPGA; sequential designs; combinational designs; pipelined designs; IDEAS synthesis system; XC3000 family; XC4000 family; dedicated carry logic; XACT tool; XBLOX tool; logic CAD (xsd:string)
dc:title A multiplier generator for Xilinx FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document