[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/SrinivasBA97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mandyam-Komar_Srinivas>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michael_L._Bushnell>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vishwani_D._Agrawal>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1997.567966>
foaf:homepage <https://doi.org/10.1109/ICVD.1997.567966>
dc:identifier DBLP conf/vlsid/SrinivasBA97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1997.567966 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mandyam-Komar_Srinivas>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michael_L._Bushnell>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vishwani_D._Agrawal>
swrc:pages 88-94 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/SrinivasBA97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/SrinivasBA97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1997.html#SrinivasBA97>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1997.567966>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document