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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/SrinivasanMEK09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ram_Krishnamurthy_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sanu_Mathew>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Suresh_Srinivasan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vasantha_Erraguntla>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI.Design.2009.69>
foaf:homepage <https://doi.org/10.1109/VLSI.Design.2009.69>
dc:identifier DBLP conf/vlsid/SrinivasanMEK09 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI.Design.2009.69 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ram_Krishnamurthy_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sanu_Mathew>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Suresh_Srinivasan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vasantha_Erraguntla>
swrc:pages 301-306 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/SrinivasanMEK09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/SrinivasanMEK09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2009.html#SrinivasanMEK09>
rdfs:seeAlso <https://doi.org/10.1109/VLSI.Design.2009.69>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document