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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/SundaramP96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lalit_M._Patnaik>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/S._Sundaram>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1996.489616>
foaf:homepage <https://doi.org/10.1109/ICVD.1996.489616>
dc:identifier DBLP conf/vlsid/SundaramP96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1996.489616 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Distributed logic simulation: time-first evaluation vs. event driven algorithms. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lalit_M._Patnaik>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/S._Sundaram>
swrc:pages 307-310 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/SundaramP96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/SundaramP96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1996.html#SundaramP96>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1996.489616>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject circuit analysis computing; logic CAD; VLSI; integrated logic circuits; parallel algorithms; distributed logic simulation; time-first evaluation algorithm; event driven algorithm; VLSI circuits; digital circuit simulation; parallel processing; distributed simulation algorithms; parallel logic simulation (xsd:string)
dc:title Distributed logic simulation: time-first evaluation vs. event driven algorithms. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document