A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/SundareswaranBD99
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/SundareswaranBD99
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Abhijit_Dharchoudhury
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/David_T._Blaauw
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Savithri_Sundareswaran
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FICVD.1999.745145
>
foaf:
homepage
<
https://doi.org/10.1109/ICVD.1999.745145
>
dc:
identifier
DBLP conf/vlsid/SundareswaranBD99
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FICVD.1999.745145
(xsd:string)
dcterms:
issued
1999
(xsd:gYear)
rdfs:
label
A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Abhijit_Dharchoudhury
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/David_T._Blaauw
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Savithri_Sundareswaran
>
swrc:
pages
175-180
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1999
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/vlsid/SundareswaranBD99/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/vlsid/SundareswaranBD99
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/vlsid/vlsid1999.html#SundareswaranBD99
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ICVD.1999.745145
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/vlsid
>
dc:
subject
assertion, assertibility, spice verification, timing analysis, primary-path, secondary-path
(xsd:string)
dc:
title
A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document