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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/ThakkarP17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ishan_G._Thakkar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sudeep_Pasricha>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSID.2017.6>
foaf:homepage <https://doi.org/10.1109/VLSID.2017.6>
dc:identifier DBLP conf/vlsid/ThakkarP17 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSID.2017.6 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ishan_G._Thakkar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sudeep_Pasricha>
swrc:pages 41-46 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2017>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/ThakkarP17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/ThakkarP17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2017.html#ThakkarP17>
rdfs:seeAlso <https://doi.org/10.1109/VLSID.2017.6>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document