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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/ThakralMGP10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dhiraj_K._Pradhan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dhruva_Ghai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Garima_Thakral>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Saraju_P._Mohanty>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI.Design.2010.14>
foaf:homepage <https://doi.org/10.1109/VLSI.Design.2010.14>
dc:identifier DBLP conf/vlsid/ThakralMGP10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI.Design.2010.14 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dhiraj_K._Pradhan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dhruva_Ghai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Garima_Thakral>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Saraju_P._Mohanty>
swrc:pages 45-50 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/ThakralMGP10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/ThakralMGP10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#ThakralMGP10>
rdfs:seeAlso <https://doi.org/10.1109/VLSI.Design.2010.14>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject SRAM, Nanoscale CMOS, Power Dissipation, Static Noise Margin (xsd:string)
dc:title A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document