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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/UsamiSHMTNSANIKN09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hideharu_Amano>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiroki_Masuda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Nakamura>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kimiyoshi_Usami>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masaaki_Kondo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masashi_Imai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mitaro_Namiki>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mitsutaka_Nakata>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Naomi_Seki>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Seidai_Takeda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tatsunori_Hashida>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Toshiaki_Shirai>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI.Design.2009.63>
foaf:homepage <https://doi.org/10.1109/VLSI.Design.2009.63>
dc:identifier DBLP conf/vlsid/UsamiSHMTNSANIKN09 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI.Design.2009.63 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hideharu_Amano>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiroki_Masuda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Nakamura>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kimiyoshi_Usami>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masaaki_Kondo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masashi_Imai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mitaro_Namiki>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mitsutaka_Nakata>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Naomi_Seki>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Seidai_Takeda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tatsunori_Hashida>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Toshiaki_Shirai>
swrc:pages 381-386 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/UsamiSHMTNSANIKN09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/UsamiSHMTNSANIKN09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2009.html#UsamiSHMTNSANIKN09>
rdfs:seeAlso <https://doi.org/10.1109/VLSI.Design.2009.63>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document