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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/WadekarCMN16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Biman_Chattopadhyay>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gopalkrishna_Nayak>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jayesh_Wadekar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ravi_Mehta>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSID.2016.90>
foaf:homepage <https://doi.org/10.1109/VLSID.2016.90>
dc:identifier DBLP conf/vlsid/WadekarCMN16 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSID.2016.90 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Biman_Chattopadhyay>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gopalkrishna_Nayak>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jayesh_Wadekar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ravi_Mehta>
swrc:pages 236-239 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2016>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/WadekarCMN16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/WadekarCMN16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2016.html#WadekarCMN16>
rdfs:seeAlso <https://doi.org/10.1109/VLSID.2016.90>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document