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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/XuG10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gary_Gr%E2%88%9A%C2%A9wal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ming_Xu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI.Design.2010.20>
foaf:homepage <https://doi.org/10.1109/VLSI.Design.2010.20>
dc:identifier DBLP conf/vlsid/XuG10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI.Design.2010.20 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label A Graph-Based I/O Pad Pre-placement Technique for Use with Analytic FPGA Placement Methods. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gary_Gr%E2%88%9A%C2%A9wal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ming_Xu>
swrc:pages 63-68 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/XuG10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/XuG10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#XuG10>
rdfs:seeAlso <https://doi.org/10.1109/VLSI.Design.2010.20>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject FPGA, Analytic Placement, I/O-Pad Pre-assignment (xsd:string)
dc:title A Graph-Based I/O Pad Pre-placement Technique for Use with Analytic FPGA Placement Methods. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document