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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsit/ChenKTK22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Carlos_Tokunaga>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gregory_K._Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Phil_C._Knag>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ram_K._Krishnamurthy>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSITechnologyandCir46769.2022.9830518>
foaf:homepage <https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830518>
dc:identifier DBLP conf/vlsit/ChenKTK22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSITechnologyandCir46769.2022.9830518 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Carlos_Tokunaga>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gregory_K._Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Phil_C._Knag>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ram_K._Krishnamurthy>
swrc:pages 68-69 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsit/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsit/ChenKTK22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsit/ChenKTK22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsit/vlsit2022.html#ChenKTK22>
rdfs:seeAlso <https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830518>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsit>
dc:title An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document