[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsit/JiangXCMDSBJCAN22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Halid_Mulaosmanovic>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hussam_Amrouch>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kai_Ni_0004>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajiv_V._Joshi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stefan_D%E2%88%9A%C4%BEnkel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Steven_Soss>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sven_Beyer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Swetaki_Chatterjee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vijaykrishnan_Narayanan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yi_Xiao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yogesh_Singh_Chauhan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhouhang_Jiang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSITechnologyandCir46769.2022.9830172>
foaf:homepage <https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830172>
dc:identifier DBLP conf/vlsit/JiangXCMDSBJCAN22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSITechnologyandCir46769.2022.9830172 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Halid_Mulaosmanovic>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hussam_Amrouch>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kai_Ni_0004>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajiv_V._Joshi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stefan_D%E2%88%9A%C4%BEnkel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Steven_Soss>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sven_Beyer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Swetaki_Chatterjee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vijaykrishnan_Narayanan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yi_Xiao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yogesh_Singh_Chauhan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhouhang_Jiang>
swrc:pages 395-396 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsit/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsit/JiangXCMDSBJCAN22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsit/JiangXCMDSBJCAN22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsit/vlsit2022.html#JiangXCMDSBJCAN22>
rdfs:seeAlso <https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830172>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsit>
dc:title Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document