A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsit/KimYCCLLLYDTLSB23
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/vlsit/KimYCCLLLYDTLSB23
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Byungho_Yook
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Changhoon_Do
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Chanho_Lee
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Dongwook_Seo
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Hoyoung_Tang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Inhak_Lee
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jeongkyun_Kim
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kyuwon_Choi
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Sangyeop_Baeck
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Seok_Yun
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Taemin_Choi
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Youngo_Lee
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Yunrong_Li
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.23919%2FVLSITechnologyandCir57934.2023.10185223
>
foaf:
homepage
<
https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185223
>
dc:
identifier
DBLP conf/vlsit/KimYCCLLLYDTLSB23
(xsd:string)
dc:
identifier
DOI doi.org%2F10.23919%2FVLSITechnologyandCir57934.2023.10185223
(xsd:string)
dcterms:
issued
2023
(xsd:gYear)
rdfs:
label
A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Byungho_Yook
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Changhoon_Do
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Chanho_Lee
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Dongwook_Seo
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Hoyoung_Tang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Inhak_Lee
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jeongkyun_Kim
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kyuwon_Choi
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Sangyeop_Baeck
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Seok_Yun
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Taemin_Choi
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Youngo_Lee
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Yunrong_Li
>
swrc:
pages
1-2
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/vlsit/2023
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/vlsit/KimYCCLLLYDTLSB23/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/vlsit/KimYCCLLLYDTLSB23
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#KimYCCLLLYDTLSB23
>
rdfs:
seeAlso
<
https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185223
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/vlsit
>
dc:
title
A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document