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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsit/ShamannaAAAABCC23>
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foaf:homepage <http://dx.doi.org/doi.org%2F10.23919%2FVLSITechnologyandCir57934.2023.10185369>
foaf:homepage <https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185369>
dc:identifier DBLP conf/vlsit/ShamannaAAAABCC23 (xsd:string)
dc:identifier DOI doi.org%2F10.23919%2FVLSITechnologyandCir57934.2023.10185369 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology. (xsd:string)
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rdfs:seeAlso <https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185369>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsit>
dc:title E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology. (xsd:string)
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rdf:type swrc:InProceedings
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