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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsit/TangCHBZCLZTWMY23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Allen_Chan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cheng-Hsun_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ching-Chi_Chang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jacob_Botimer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Junkang_Zhu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mani_Yalamanchi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mark_Flannigan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Naomi_Kavi_Motwani>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ramya_Yarlagadda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sergey_Y._Shumarayev>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sirisha_Kale>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sung-Gun_Cho>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thungoc_Tran>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tianyu_Wei>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tim_Tri_Hoang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei_Qiang_Zhu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei_Tang_0010>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yaoyu_Tao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhengya_Zhang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.23919%2FVLSITechnologyandCir57934.2023.10185388>
foaf:homepage <https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185388>
dc:identifier DBLP conf/vlsit/TangCHBZCLZTWMY23 (xsd:string)
dc:identifier DOI doi.org%2F10.23919%2FVLSITechnologyandCir57934.2023.10185388 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Allen_Chan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cheng-Hsun_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ching-Chi_Chang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jacob_Botimer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Junkang_Zhu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mani_Yalamanchi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mark_Flannigan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Naomi_Kavi_Motwani>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ramya_Yarlagadda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sergey_Y._Shumarayev>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sirisha_Kale>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sung-Gun_Cho>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thungoc_Tran>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tianyu_Wei>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tim_Tri_Hoang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei_Qiang_Zhu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei_Tang_0010>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yaoyu_Tao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhengya_Zhang>
swrc:pages 1-2 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsit/2023>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsit/TangCHBZCLZTWMY23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsit/TangCHBZCLZTWMY23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#TangCHBZCLZTWMY23>
rdfs:seeAlso <https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185388>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsit>
dc:title Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document