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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Baoyong_Chi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bufan_Zhu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chao_Tang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Haikun_Jia>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hongzhuo_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shiyan_Sun>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei_Deng_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu_Fu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.23919%2FVLSITechnologyandCir57934.2023.10185335>
foaf:homepage <https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185335>
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dc:identifier DOI doi.org%2F10.23919%2FVLSITechnologyandCir57934.2023.10185335 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/őľs Chirp Slope. (xsd:string)
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bufan_Zhu>
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Haikun_Jia>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hongzhuo_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shiyan_Sun>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei_Deng_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu_Fu>
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rdfs:seeAlso <https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185335>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsit>
dc:title An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/őľs Chirp Slope. (xsd:string)
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rdf:type swrc:InProceedings
rdf:type foaf:Document