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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsit/ZhangZCQLWL23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jian_Liu_0021>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Liyuan_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nan_Qi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nanjian_Wu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yong_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhao_Zhang_0004>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhaoyu_Zhang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.23919%2FVLSITechnologyandCir57934.2023.10185285>
foaf:homepage <https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185285>
dc:identifier DBLP conf/vlsit/ZhangZCQLWL23 (xsd:string)
dc:identifier DOI doi.org%2F10.23919%2FVLSITechnologyandCir57934.2023.10185285 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jian_Liu_0021>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Liyuan_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nan_Qi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nanjian_Wu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yong_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhao_Zhang_0004>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhaoyu_Zhang>
swrc:pages 1-2 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsit/2023>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsit/ZhangZCQLWL23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsit/ZhangZCQLWL23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#ZhangZCQLWL23>
rdfs:seeAlso <https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185285>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsit>
dc:title A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document