An Efficient VLSI Architecture of a Layered Space-Time Receiver. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Isabelle_LaRoche>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/S%E2%88%9A%C2%A9bastien_Roy_0002>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FVETECS.2007.91>
foaf:homepage	<https://doi.org/10.1109/VETECS.2007.91>
dc:identifier	DBLP conf/vtc/LaRocheR07 (xsd:string)
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dcterms:issued	2007 (xsd:gYear)
rdfs:label	An Efficient VLSI Architecture of a Layered Space-Time Receiver. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Isabelle_LaRoche>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/S%E2%88%9A%C2%A9bastien_Roy_0002>
swrc:pages	387-391 (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/vtc/vtc2007s.html#LaRocheR07>
rdfs:seeAlso	<https://doi.org/10.1109/VETECS.2007.91>
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dc:title	An Efficient VLSI Architecture of a Layered Space-Time Receiver. (xsd:string)
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