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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vts/BarbagalloBMCPR96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Davide_Medina>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fulvio_Corno>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Matteo_Sonza_Reorda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Monica_Lobetti_Bodoni>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paolo_Prinetto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stefano_Barbagallo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVTEST.1996.510831>
foaf:homepage <https://doi.org/10.1109/VTEST.1996.510831>
dc:identifier DBLP conf/vts/BarbagalloBMCPR96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVTEST.1996.510831 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Scan insertion criteria for low design impact. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Davide_Medina>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fulvio_Corno>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Matteo_Sonza_Reorda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Monica_Lobetti_Bodoni>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paolo_Prinetto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stefano_Barbagallo>
swrc:pages 26-31 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vts/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vts/BarbagalloBMCPR96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vts/BarbagalloBMCPR96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vts/vts1996.html#BarbagalloBMCPR96>
rdfs:seeAlso <https://doi.org/10.1109/VTEST.1996.510831>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vts>
dc:subject boundary scan testing; automatic testing; integrated circuit testing; logic testing; sequential circuits; flip-flops; capacitance; integrated circuit design; application specific integrated circuits; logic CAD; scan insertion criteria; design impact; partial scan; full scan; flip-flop ordering; scan chain; capacitance constraints; layout information; design flow; power dissipation; Italtel Design Environment (xsd:string)
dc:title Scan insertion criteria for low design impact. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document