A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/ChunKKK09
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A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections.
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A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections.
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