A new test pattern generation method for delay fault testing.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/CremouxFGLP96
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1996
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A new test pattern generation method for delay fault testing.
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VLSI; built-in self test; integrated circuit testing; delays; logic testing; learning (artificial intelligence); automatic testing; digital integrated circuits; test pattern generation method; delay fault testing; high speed circuits; directed random generation technique; random test vectors; learning tool; test sequence length; delay fault coverage; BIST
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A new test pattern generation method for delay fault testing.
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