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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vts/De97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kaushik_De>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVTEST.1997.599434>
foaf:homepage <https://doi.org/10.1109/VTEST.1997.599434>
dc:identifier DBLP conf/vts/De97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVTEST.1997.599434 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label Test methodology for embedded cores which protects intellectual property. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kaushik_De>
swrc:pages 2-9 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vts/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vts/De97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vts/De97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vts/vts1997.html#De97>
rdfs:seeAlso <https://doi.org/10.1109/VTEST.1997.599434>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vts>
dc:subject logic testing; embedded cores; test methodology; intellectual property protection; core I/Os; ASIC I/O inaccessibility; partial netlist generation; structural analysis; ASIC level test generation; gate testing; core scan chain; selective boundary scan; coreware design paradigm; heuristic algorithm (xsd:string)
dc:title Test methodology for embedded cores which protects intellectual property. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document