On estimating bounds of the quiescent current for IDDQ testin.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vts/FerreF96
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1996
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On estimating bounds of the quiescent current for IDDQ testin.
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CMOS integrated circuits; integrated circuit testing; automatic testing; VLSI; leakage currents; logic testing; quiescent current bounds; I/sub DDQ/ testing; sensing circuitry design; hierarchical approach; ATPG; CMOS ICs
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On estimating bounds of the quiescent current for IDDQ testin.
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